1. Field of the Invention
The present invention relates to a heterojunction bipolar transistor (hereafter, referred to as an "HBT") and to a method for fabricating the same. More particularly, the present invention relates to an HBT which can be fabricated with ease, shows a low leakage current between its emitter and base, and has excellent high frequency characteristics, and to a method for fabricating such an HBT.
2. Description of Related Art
HBTs provide numerous advantages in providing high performance transistors. For example, they can retain high emitter injection efficiency even when impurities are doped in high concentrations in the base by the use of a semiconductor material for the emitter layer whose bandgap is greater than that of the base layer, they can take the best use of excellent electron transport inherent to compound semiconductors, and so on.
Compound semiconductor HBTs are fabricated generally by epitaxially growing desired semiconductor layers including an emitter layer, a base layer, and a collector layer on a semiconductor substrate whose (100) plane is taken as a main surface, etching some of the semiconductor layers thus obtained to form a mesa structure, and forming ohmic contacts on the emitter, base, and collector layers.
FIG. 1 shows an example of a conventional HBT. In FIG. 1, reference numeral 31 designates a semi-insulate InP (100) substrate, 32 is an n.sup.+ -InGaAs collector contact layer, 33 is an n.sup.- -doped or undoped InGaAs collector layer, 34 is a p.sup.+ -InGaAs base layer, 35 is an n.sup.- -InP emitter layer, 36 is an n.sup.+ -InGaAs emitter contact layer, 37 is an emitter electrode, and 38 is a base electrode. The HBT shown in FIG. 1 comprises the semi-insulate substrate 31, which has deposited thereon the collector contact layer 32, the collector layer 33, and the base layer 34. In its emitter region, the HBT has the emitter layer 35, the emitter contact layer 36, and the emitter electrode 37, with these layers being arranged such that an under-cut is formed underneath the peripheral portion of the emitter electrode 37 as a result of emitter mesa etching and isotropic wet etching. The HBT also includes the base electrode 38 deposited on the base layer 34 and the emitter electrode 37.
In the conventional HBT, as shown in FIG. 1, the crystal orientation of the emitter region in the (100) plane is oriented in a direction parallel to the [011] or [01 1] direction (herein, in the expression of plane or Miller indices, negative indices are indicated by underlining). This means that when a semiconductor substrate 31 having a (100) plane in a main surface is used, its orientation flat is selected so as to be in the (011) plane where cleave facets tend to appear, i.e., in the direction parallel to the [01 1] direction and it has been considered natural to set the direction of arranging the emitter so that it is parallel or vertical to the orientation flat thereof.
Next, problems will be described which may arise when the crystal orientation of the emitter is arranged in the (100) plane in the direction conventionally used, referring to a cross-sectional structure of the device.
In order to make the best use of the inherent potential of HBTs and reach extremely high performance levels, it is necessary to reduce the parasitic effects, that is, to lower ohmic resistances and parasitic capacitances, and various self alignment structures have been proposed. Japanese Patent Application Laying-open No. 136159/1993 and IEICE Trans. Electron. Vol. E76-C, No. 9 Sep., 1993, pp. 1392-1401 disclose self-aligned HBT structures with considerably low parasitic resistances and parasitic capacitances as well as with excellent uniformity and reproducibility and methods for fabricating such structures. According to these technologies, the emitter electrode is formed in advance and emitter mesa etching is performed with an etchant which etches the emitter layer selectively until the base layer is exposed using the emitter electrode as a mask, and at the same time an under-cut is formed underneath the peripheral portion of the emitter electrode utilizing the isotropic nature of wet etching. Thereafter, a base electrode material is deposited on the surface of the substrate in the region including the emitter mesa. The above-described structures and methods allow self-alignment of the emitter and base electrodes without a short because of the provision of an under-cut. Furthermore, with the structures and methods, it is easy to make the base electrode narrower, which is advantageous in reducing the contact area between the base and collector.
However, control of the crystal orientation of the emitter only in a direction parallel to the [01 1] or [011] direction raises a problem in relation to the anisotropy of the crystal upon wet etching. That is, as shown in FIG. 1, the emitter mesa structure formed by wet etching is in the form of a trapezoid with its lower edge being shorter, i.e., in the form of an under-cut mesa structure, in a cross-sectional view taken along the direction parallel to the [01 1] direction, i.e., as viewed in the (011) plane. On the contrary, as viewed in a cross-section along a direction parallel to the [011] direction, i.e., in the (0 11) plane, the emitter mesa is in the form of a trapezoid with its upper edge being shorter, i.e., in the form of an outwardly slanted structure. The use of selective etching results in that the etching proceeds along a vertical direction so that after the base layer 34 is exposed, side etching along the [011] direction does not proceed substantially. Under these conditions, the method for fabricating a self-alignment structure by the deposition of a metal for the formation of the base electrode on the surface of the semiconductor substrate in the region including the emitter mesa gives a structure in which the base electrode 38 tends to contact the emitter layer 35 in a cross-section of an outwardly slant form. If the base electrode 38 contacts the emitter layer 35, leakage current which flows between the emitter and base increases to thereby reduce the current gain. In some cases, an E/B short occurs between the electrode 38 and the emitter electrode 37, so that the device cannot operate at all as a transistor.
A method has been proposed which is intended to form an under-cut reliably as viewed also in the cross-section along the (0 11) plane, by using anisotropic dry etching and selective wet etching in combination in a desired manner. However, this approach has also a problem in that the process is not fully reproducible and controllable. Thus, in order to establish a reliable electric isolation between the emitter and base, the time of etching in a selective etching procedure needs to be prolonged to thereby increase the amount of the under-cut. In this occasion, the proportions of the base resistance and base/collector junction area to the emitter/base junction area increase, respectively, so that the high frequency operation of the transistor is damaged. This is worse as the transistor is smaller in scale because it is intended to operate at a high performance.
Japanese Patent Application Laying-open No. 48078/1993 discloses an AlGaAs/GaAs heterojunction bipolar transistor which has an HBT structure with a Be-doped base layer and an emitter region containing no orientation flat that is parallel to the [011] direction. At column 4, lines 43 to 47, there is a description to the effect that a difference in the shape of the emitter mesa gives rise to a difference in a stress applied to the interface between the surface protection insulator and an edge of the emitter mesa, so that the diffusion of Be upon application of current depends on the direction in which the emitter is formed. Further, at column 6, line 36, it also describes that the emitter is of a structure which has a long under-cut mesa edge and in which no outward slant shape appears, so that the diffusion of the impurities doped in the base layer upon application of current can be prevented in the vicinity of the outward slant edge and, hence, heterojunction bipolar transistors can be fabricated which have a very low variation in characteristics when they are operated at high current densities. FIG. 4 in the above-mentioned publication shows a structure in which the emitter is hexagonal and its longest edge is in a direction parallel to the [011] direction, with the extrinsic base layer and the base electrode surrounding the emitter mesa. This HBT structure is not self-aligned so that it cannot be applied to high performance, small-scale transistors.
Japanese Patent Application Laying-open No. 243258/1993 relates to a self-aligned InP/GaInAs based HBT in which the emitter is arranged such that one of the edges of the emitter is parallel to the [001] direction or perpendicular thereto and both ohmic electrodes are formed at the same time on the emitter cap and on the base. In this case, in order to make an under-cut utilizing the emitter cap as a mask, the same metal material is used for forming the emitter electrode and the base electrode.